實體攻擊示範Physical demonstration
有目標晶片、設備、程序與恢復結果。Target chip, equipment, procedure and recovered result.
EVIDENCE LEDGER · PAPERS · PATENTS · PRODUCT DISCLOSURES
不是來源清單
是證據邊界Not a reading list
An evidence boundary
每一筆資料都回答三件事：它直接證明什麼、不能證明什麼，以及它在 Secure Storage 論述中應該站在哪一層。Every record states what it directly supports, what it does not establish, and where it belongs in the Secure Storage argument.
EVIDENCE CLASS · NOT ASSURANCE MATURITY
Claim → Evidence → Inference，
不跨級偷換Claim → Evidence → Inference,
without category errors
這裡分類「來源如何支持主張」，不同於 Assurance Center 的 M1–M6 成熟度。專利用於證明 sensing topology 的存在；供應商文件描述自家 architecture 與測試主張；攻擊難度與普遍性只由獨立實證支撐。This classifies how a source supports a claim; it is distinct from the Assurance Center's M1–M6 maturity. Patents establish that a sensing topology exists; vendor documents describe their architecture and test claims; only independent demonstrations support attack feasibility and generality.
電路與物理Circuit and physics
說明 read、leakage、breakdown 或 sensing 如何發生。Explains how read, leakage, breakdown or sensing occurs.
產品公開主張Product disclosure
可引用，但需標記為供應商自己提供的證據。Citable with explicit attribution as vendor-provided evidence.
系統級結論System inference
由多筆來源組成，仍需產品或節點實測封閉。Composed from sources and closed only by product/node validation.
ANNOTATED SOURCE CORPUS
查證每一句話，
也查證它的限制Verify every sentence—
and its limit
使用搜尋或類型篩選。關鍵詞同時涵蓋 technology、attack、author、DOI、PUF、sense amplifier、photon emission、FIB 與 product architecture。Search or filter by source type. Keywords cover technology, attack, author, DOI, PUF, sense amplifiers, photon emission, FIB and product architecture.
31 筆符合目前條件records match the current viewPUBLIC SOURCES · ACCESSED 2026-08-12
P01PEER-REVIEWED
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Holcomb、Burleson 與 Fu 建立 SRAM power-up fingerprint 的實驗基礎，將 device identity 連結到 MOSFET threshold mismatch 與 startup noise。Holcomb, Burleson and Fu establish the experimental basis for SRAM power-up fingerprints rooted in MOSFET threshold mismatch and startup noise.
支持 (SUPPORTS)SUPPORTS
SRAM PUF 的物理來源與 power-up expression。Physical origin and power-up expression of SRAM PUF.
不證明 (DOES NOT PROVE)DOES NOT PROVE
特定商用 PUF 的完整攻擊抵抗力。Full attack resistance of a commercial PUF.
P02PEER-REVIEWED
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM
提出 SRAM current-mode sense amplifier，直接反證「SRAM 本質上只能 voltage sensing」。Presents a current-mode SRAM sense amplifier, directly disproving that SRAM is inherently voltage-sense only.
支持 (SUPPORTS)SUPPORTS
Sense mode 是 circuit choice。Sense mode is a circuit choice.
不證明 (DOES NOT PROVE)DOES NOT PROVE
任何特定 SRAM macro 採用此 topology。That a specific SRAM macro uses it.
T01PATENT
High Speed OTP Sensing Scheme
Sidense 專利揭露 twin-cell differential arrangement：一對 cell 中恰有一個被 programming，以 complementary bitline 的 voltage difference 進行正常讀取。Sidense discloses a twin-cell differential arrangement with exactly one programmed cell per pair and normal read through complementary-bitline voltage difference.
支持 (SUPPORTS)SUPPORTS
1T twin-cell、真正互補 representation 與 differential read 的技術基礎。The technical basis for 1T twin-cell complementary representation and differential read.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有 Synopsys macro 的預設設定或精確 macro area。The default configuration of every Synopsys macro or exact macro area.
T02PATENT
Current Sensing Amplifier for SRAM
Intel 專利將 SRAM bitline voltage differential 轉為 current differential，再轉回放大的 voltage output。Intel's patent converts SRAM bitline voltage differential to current differential and then back to an amplified voltage output.
支持 (SUPPORTS)SUPPORTS
Voltage/current 是連續 read chain 的不同節點。Voltage/current are nodes on one read chain.
不證明 (DOES NOT PROVE)DOES NOT PROVE
current-mode 比 voltage-mode 更不安全或更安全。That current mode is more or less secure.
P03ATTACK STUDY
Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out
在商用 MSP430 比較 Photon Emission、TLS 與 EOFM，說明 SRAM content readout 對 core voltage 與 modulation 條件的依賴。Compares Photon Emission, TLS and EOFM on a commercial MSP430, showing SRAM readout dependence on core voltage and modulation.
支持 (SUPPORTS)SUPPORTS
三類 optical failure-analysis technique 可讀 SRAM。Three optical FA techniques can read SRAM.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有節點與封裝都有相同 SNR。Equal SNR across nodes and packages.
P04ATTACK STUDY
Direct Read of Idle Block RAM from FPGAs Utilizing Photon Emission Microscopy
以 SRAM cell 內 state-dependent NMOS leakage photon 直接讀取 idle FPGA block RAM，不需啟動正常 read circuitry。Reads idle FPGA block RAM through state-dependent NMOS leakage photons without activating normal read circuitry.
支持 (SUPPORTS)SUPPORTS
SRAM 靜態 state 也可能形成位置可辨光子訊號。Static SRAM state can create spatially distinguishable photons.
不證明 (DOES NOT PROVE)DOES NOT PROVE
斷電且無 remanence 時仍能讀 0/1。0/1 recovery after power-off without remanence.
P05ATTACK STUDY
Quiescent Photonics Side Channel Analysis: Low-Cost SRAM Readout Attack
在 PIC 與 ARM Cortex-M0 展示 quiescent photon differential analysis，並提出較低成本的 sample preparation 與 imaging setup。Demonstrates quiescent photon differential analysis on PIC and ARM Cortex-M0 devices with lower-cost preparation and imaging.
支持 (SUPPORTS)SUPPORTS
光子側信道不只存在於高階實驗室。Photon side channels are not limited to top-tier labs.
不證明 (DOES NOT PROVE)DOES NOT PROVE
對所有 advanced node 都低成本。Low cost on every advanced node.
P06ATTACK STUDY
Key Extraction Using Thermal Laser Stimulation: Xilinx UltraScale FPGAs
從 battery-backed SRAM 以一次非侵入量測恢復 256-bit AES key，並討論 power-off TLS countermeasure。Recovers a 256-bit AES key from battery-backed SRAM in one non-invasive measurement and presents a power-off TLS countermeasure.
支持 (SUPPORTS)SUPPORTS
把 key 放在 powered SRAM 並不免疫 failure-analysis tools。Powered SRAM key storage is not immune to FA tools.
不證明 (DOES NOT PROVE)DOES NOT PROVE
等同攻破 SRAM PUF reconstruction。Equivalence to breaking SRAM-PUF reconstruction.
P07ATTACK STUDY
Low Temperature Data Remanence in Static RAM
實驗建立現代 SRAM retention time 與低溫的關係，挑戰「斷電即消失」的簡化假設。Experimentally relates SRAM retention time to low temperature, challenging the simplified “power-off means immediate loss” assumption.
支持 (SUPPORTS)SUPPORTS
Volatile 不等於零 remanence window。Volatile does not mean zero remanence window.
不證明 (DOES NOT PROVE)DOES NOT PROVE
正常環境下 SRAM 長期保留。Long-term SRAM retention at normal conditions.
P08ATTACK STUDY
Attacking SRAM PUFs Using Very-Low-Temperature Data Remanence
研究 −110°C 至 −40°C 的 intrinsic SRAM PUF remanence，顯示攻擊者可高機率得知 response，並討論 countermeasure。Studies intrinsic SRAM-PUF remanence from −110°C to −40°C, showing high-probability response recovery and discussing countermeasures.
支持 (SUPPORTS)SUPPORTS
SRAM PUF 的「absent」需要正常條件邊界。“Absent” needs a normal-conditions boundary.
不證明 (DOES NOT PROVE)DOES NOT PROVE
商用 IP 未採取偵測或抵抗措施。That commercial IP lacks detection or resistance.
P09ATTACK STUDY
Extraction of Secrets from 40 nm CMOS Gate-Dielectric-Breakdown Antifuses by FIB PVC
在 RP2350 類 40 nm commodity MCU 示範 FIB passive voltage contrast 擷取 antifuse OTP，並量化 sample preparation 與分析時間。Demonstrates FIB passive-voltage-contrast extraction of antifuse OTP on a 40 nm commodity MCU and reports preparation/analysis effort.
支持 (SUPPORTS)SUPPORTS
Antifuse 不應被視為不可讀的明文 key vault。Antifuse should not be treated as an unreadable plaintext key vault.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有 antifuse macro 成本相同或都能完整逐 bit 恢復。Equal cost or complete bit recovery for every antifuse macro.
P10ATTACK STUDY
Reverse Engineering Flash EEPROM Memories Using Scanning Electron Microscopy
backside preparation 後以 SEM passive voltage contrast 區分 floating-gate cell 0/1，並示範自動化 full-memory acquisition。Uses SEM passive voltage contrast after backside preparation to distinguish floating-gate 0/1 and automate full-memory acquisition.
支持 (SUPPORTS)SUPPORTS
Persistent charge 也能成為 failure-analysis contrast。Persistent charge can become FA contrast.
不證明 (DOES NOT PROVE)DOES NOT PROVE
與 antifuse、eFuse 攻擊程序完全相同。Identical procedure for antifuse or eFuse.
P11PEER-REVIEWED
Balancing the Leakage Currents in Nanometer CMOS Logic—A Challenging Goal
分析 nanometer CMOS data-dependent static leakage 與 countermeasure，支持「靜態 CMOS 也有 current side channel」。Analyzes data-dependent static leakage in nanometer CMOS and countermeasures, supporting that static CMOS also has a current side channel.
支持 (SUPPORTS)SUPPORTS
靜態 power signature 與邏輯狀態相關。Static power signatures can depend on logic state.
不證明 (DOES NOT PROVE)DOES NOT PROVE
特定 memory array 可直接影像化。Direct imaging of a specific memory array.
T03PATENT
Protecting Against Emission-Based Side-Channel Detection
以 SRAM static photon emission、EOFM/LVI 等威脅為出發點提出 countermeasure，說明 industry 將此視為實際設計問題。Proposes countermeasures against SRAM static photon emission and EOFM/LVI, showing that industry treats it as a design concern.
支持 (SUPPORTS)SUPPORTS
SRAM emission attack 有專利級防禦需求。SRAM emission attacks motivate patent-level defenses.
不證明 (DOES NOT PROVE)DOES NOT PROVE
某產品已實作該 countermeasure。That a product implements the countermeasure.
T04PATENT
System for Generating a Cryptographic Key from a Memory Used as a PUF
討論 photonic-emission 對 SRAM PUF first-read/power-up content 的潛在攻擊與防護概念。Discusses potential photonic-emission attacks on first-read/power-up SRAM-PUF contents and protective concepts.
支持 (SUPPORTS)SUPPORTS
「key 不永久儲存」仍需保護 response capture。A non-stored key still requires response-capture protection.
不證明 (DOES NOT PROVE)DOES NOT PROVE
攻擊可繞過現代商用 PUF 全部 countermeasure。Bypass of all modern commercial-PUF countermeasures.
V01VENDOR BOOK
Quantum Tunneling PUF: Basics, Circuits, and Security Applications
描述 NeoPUF enrollment、永久 tunneling path、single-ended Icell/Iref sensing、SEM/TEM 與 InGaAs 測試，以及其對 SRAM PUF 的比較。Describes NeoPUF enrollment, persistent tunneling paths, single-ended Icell/Iref sensing, SEM/TEM and InGaAs tests, and comparison with SRAM PUF.
支持 (SUPPORTS)SUPPORTS
NeoPUF 自述機制與內部測試結果。NeoPUF's disclosed mechanism and internal tests.
不證明 (DOES NOT PROVE)DOES NOT PROVE
第三方獨立重現或所有節點免疫。Independent replication or immunity across nodes.
V02PRODUCT PAGE
Secure Storage Solution for OTP IP
公開架構：antifuse OTP、SRAM PUF power-up root、AES-256 engine、address scrambling、Secure Controller、APB 與 automatic provisioning。Discloses antifuse OTP, SRAM-PUF power-up root, AES-256 engine, address scrambling, Secure Controller, APB and automatic provisioning.
支持 (SUPPORTS)SUPPORTS
產品 scope、interfaces 與公開 benefit。Product scope, interfaces and disclosed benefits.
不證明 (DOES NOT PROVE)DOES NOT PROVE
未公開 crypto mode、integrity 與 attack-test 細節。Undisclosed crypto mode, integrity and attack-test details.
V03TECHNICAL ARTICLE
Strengthening Silicon-Level Security with the Secure Storage Solution for OTP IP
把 FIB／physical access 與 antifuse plaintext risk 轉成 encrypted OTP + non-stored root 的 layered-defense 主張。Frames FIB/physical access and antifuse plaintext risk as a layered-defense case for encrypted OTP and a non-stored root.
支持 (SUPPORTS)SUPPORTS
產品設計意圖與威脅敘事。Product design intent and threat narrative.
不證明 (DOES NOT PROVE)DOES NOT PROVE
完整 security proof 或特定 attacker cost。A complete security proof or attacker cost.
V04TECHNICAL ARTICLE
Understanding SRAM PUF: The Secure Silicon Fingerprint
說明 uninitialized SRAM、Activation Code 儲存位置、key on-demand extraction，以及斷電時 key 不存在的產品模型。Explains uninitialized SRAM, Activation Code storage, on-demand key extraction and the product model in which the key is absent at power-off.
支持 (SUPPORTS)SUPPORTS
Synopsys SRAM PUF lifecycle 與 integration requirements。Synopsys SRAM-PUF lifecycle and integration requirements.
不證明 (DOES NOT PROVE)DOES NOT PROVE
Activation Code 的完整 leakage/integrity proof。Complete leakage/integrity proof for the Activation Code.
V05DATASHEET
Secure OTP — Tamperproof Storage Datasheet
公開 1024-bit PUF、physical address scrambling、I/O shuffling、APB、permission／zeroization／lock 與 instant hardware encryption 等產品主張。Discloses a 1024-bit PUF, physical address scrambling, I/O shuffling, APB, permission/zeroization/lock and instant hardware-encryption claims.
支持 (SUPPORTS)SUPPORTS
Secure OTP 公開功能範圍。Public Secure OTP feature scope.
不證明 (DOES NOT PROVE)DOES NOT PROVE
crypto algorithm／mode 與完整 independent attack evidence。Crypto algorithm/mode or independent attack evidence.
P12FOUNDRY PAPER
A 16Kb 5nm Antifuse One-Time Programmable Memory with Pseudo-Differential Sensing
TSMC 公開 5 nm antifuse OTP macro，採 bootstrap high voltage、read endpoint detection 與 pseudo-differential sensing，並報告高溫十年 retention 目標。TSMC discloses a 5 nm antifuse OTP macro using bootstrap high voltage, read-endpoint detection and pseudo-differential sensing with a ten-year high-temperature retention target.
支持 (SUPPORTS)SUPPORTS
先進節點 antifuse 與 pseudo-differential sensing 的實作可行性。Feasibility of advanced-node antifuse and pseudo-differential sensing.
不證明 (DOES NOT PROVE)DOES NOT PROVE
商用 macro 的預設安全模式或特定 IP 授權合約。A commercial macro's default security mode or a specific IP license contract.
T05PATENT
Antifuse-Type One-Time Programmable Memory Cell and Array
eMemory 專利的傳統 cell 圖示包含 select transistor 與 antifuse transistor／capacitor device，提供「select device + programming device」成本模型的一手依據。eMemory's conventional cell drawing includes a select transistor and an antifuse transistor/capacitor device, providing primary support for the select-device-plus-programming-device cost model.
支持 (SUPPORTS)SUPPORTS
為何真正 complementary pair 會增加 cell 與 routing burden。Why a true complementary pair adds cell and routing burden.
不證明 (DOES NOT PROVE)DOES NOT PROVE
每一代 NeoFuse 都採完全相同 topology，或可用 transistor ratio 推算 macro area。That every NeoFuse generation uses the same topology or that transistor ratio predicts macro area.
V06OFFICIAL NEWS
Synopsys Acquires Sidense Corporation
Synopsys 官方收購公告明列 Sidense patented split-channel 1T-Fuse、低功耗／小面積、最快 10 ns read 與 volume-production 紀錄。Synopsys' acquisition release explicitly cites Sidense's patented split-channel 1T-Fuse, low power/small area, reads as fast as 10 ns and volume-production history.
支持 (SUPPORTS)SUPPORTS
1T-Fuse 的官方技術血統與 2017 收購年份。Official 1T-Fuse lineage and the 2017 acquisition date.
不證明 (DOES NOT PROVE)DOES NOT PROVE
每個後續 macro 都沿用相同 read configuration。That every later macro uses the same read configuration.
V07TECHNICAL ARTICLE
Ensuring Reliable, Secure OTP IP in Advanced Nodes
Synopsys 公開說明其 OTP「可配置」為 differential read mode，以提高由 power signature 辨識內容的難度。Synopsys publicly states that its OTP can be configured in differential read mode to make content identification from power signature more difficult.
支持 (SUPPORTS)SUPPORTS
Differential read 是現行商業 feature 與安全選項。Differential read is a current commercial feature and security option.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有 macro 預設開啟、完全消除 optical/FIB leakage，或精確 PPA impact。Default enablement on every macro, elimination of optical/FIB leakage, or exact PPA impact.
V08OFFICIAL NEWS
Synopsys Acquires Kilopass Technology
官方公告確認 Kilopass 收購日期為 2018-01-10，並列出 1T／2T bitcell portfolio、10／7 nm silicon-proven 與超過 100 億顆出貨紀錄。The official release dates the Kilopass acquisition to 2018-01-10 and cites a 1T/2T portfolio, silicon-proven 10/7 nm offerings and more than 10 billion units shipped.
支持 (SUPPORTS)SUPPORTS
Kilopass advanced-node 能力、產品範圍與正確收購年份。Kilopass advanced-node capability, product scope and correct acquisition year.
不證明 (DOES NOT PROVE)DOES NOT PROVE
TSMC 特定 in-house macro 的授權條款或電路完全相同。Licensing terms or circuit identity for a specific TSMC in-house macro.
V09FOUNDRY NEWS
Kilopass XPM Qualified on TSMC 0.18 µm Process
TSMC 官方新聞記錄 Kilopass XPM 在 TSMC 製程完成 qualification，建立雙方公開可追溯的早期合作關係。TSMC's official release records Kilopass XPM qualification on a TSMC process, establishing an early, publicly traceable relationship.
支持 (SUPPORTS)SUPPORTS
TSMC／Kilopass 的歷史合作與技術血統。Historical TSMC/Kilopass collaboration and technology lineage.
不證明 (DOES NOT PROVE)DOES NOT PROVE
10 nm 以下授權合約、延續條款或 5 nm macro 的直接來源。Sub-10 nm licensing terms, continuity clauses or the direct origin of the 5 nm macro.
V10供應商揭露VENDOR DISCLOSURE
How eNVM Helps Power Controllers Be Smarter
eMemory 的原作者文章區分固定微調用 OTP 與可更新控制資料用 NeoMTP；NeoMTP 屬浮動閘 MTP。文中分別說明零額外光罩設計與採額外光罩縮小單元的後續版本，成本、耐久度及保存條件須綁定具名 IP、版本與製程驗證。 eMemory's author article distinguishes OTP for fixed trimming from NeoMTP for updateable control data; NeoMTP is floating-gate MTP. It describes a zero-mask design and a later version with additional masks for a smaller cell. Cost, endurance and retention require validation for the named IP, version and process.
支持 (SUPPORTS)SUPPORTS
OTP 與浮動閘 NeoMTP 的用途分流，以及具名 BCD 版本的製程整合與光罩取捨。Separate roles for OTP and floating-gate NeoMTP, plus process integration and mask tradeoffs for named BCD versions.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有 OTP 與 NeoMTP 版本共用相同物理機制、零光罩條件或高溫保存保證；PPA 與可靠度仍須依具名 IP 和晶圓廠 PDK 驗證。A common physical mechanism, zero-mask condition or high-temperature retention guarantee for every OTP and NeoMTP version; PPA and reliability still require named-IP and foundry-PDK validation.
V11INDUSTRY STANDARD
JESD79-5 DDR5 & JESD238 HBM3e: Mandatory Post-Package Repair (PPR) Architecture
JEDEC 官方標準規範確立：在伺服器 DDR5 與高頻寬記憶體 (HBM3/HBM3e) 中，必須具備硬體封裝後現場修復 (hPPR) 機制。高密度 AntiFuse OTP 提供永久、零金屬回彈的非揮發性重映射位址儲存，替代傳統封裝後無法修復的雷射熔斷 (Laser Fuse)。 JEDEC specifications mandate Hard Post-Package Repair (hPPR) across DDR5 and HBM3/HBM3e. High-density AntiFuse OTP provides non-volatile, zero-growback address remapping, replacing legacy laser fuses that cannot operate post-packaging.
支持 (SUPPORTS)SUPPORTS
AntiFuse OTP 是高密度記憶體封裝後現場修復的 JEDEC 業界規範標準解決方案。AntiFuse OTP is the standard JEDEC architectural solution for in-field post-package memory repair.
不證明 (DOES NOT PROVE)DOES NOT PROVE
備援行/列可無限次替代；修復容量仍受限於實體備援數量與巨集佈局邊界。Infinite spare row/column capacity; repair boundary is governed by physical spare layout limits.
V12TECHNICAL DISCLOSURE
High-Voltage Display Driver IC Optical Uniformity: De-Mura LUT & Gamma 2.2 Calibration
顯示技術學會 (SID) 與業界高壓 DDIC 論文揭露：AMOLED 螢幕因有機發光層厚度與驅動 TFT 閾值電壓離散，原始均勻度僅 70%~75%。透過在驅動 IC 內嵌 32Kb 至 128Kb MTP 儲存二維 Gain LUT，可將顯示均勻度拉升至 99% 以上，並將 Delta E 壓制在 0.5 以內。 SID and IEEE DDIC disclosures confirm that raw AMOLED panels exhibit 70%-75% optical uniformity due to TFT mobility and OLED layer variance. Embedding 32Kb-128Kb MTP within the driver IC to store 2D Gain LUTs elevates display uniformity beyond 99% and crushes Delta E below 0.5.
支持 (SUPPORTS)SUPPORTS
高壓 AMOLED 驅動晶片必須依賴高密度 eNVM 儲存光學補償查找表與 Gamma 校準碼。High-voltage AMOLED DDICs mandate dense eNVM for optical compensation LUTs and Gamma trims.
不證明 (DOES NOT PROVE)DOES NOT PROVE
靜態 LUT 能完全解決動態螢幕老化問題；動態老化仍需配合即時電流傳感閉環算法。Static LUT eliminates dynamic panel burn-in; real-time current sensing is required for aging.
V13MARKET & TECHNICAL SURVEY
E-Ink Ultra-HV Driving & MTP-to-OTP Product Lifecycle: 40V-50V Pulse & Waveform LUT
內部市場調查與領導驅動晶片廠商（天鈺 Fitipower、晶宏 UltraChip、晶門 Solomon）技術會議揭露：電子紙微膠囊電泳需 40V-50V（110HV/90HV）高壓脈衝，標準 BCD 因接面漏電過高無法採用。黑白邁向四色與全彩（Spectra 6/Kaleido 3）演進期採用 32Kb-64Kb MTP 儲存動態波形；成熟期為追求極致成本與 <250µm 窄高佈局全面轉入純邏輯 OTP。 Industry survey and design house disclosures (Fitipower, UltraChip, Solomon) confirm that electrophoretic displays require 40V-50V (110HV/90HV) pulses, precluding standard BCD due to excessive junction leakage. The color transition era mandates 32Kb-64Kb MTP for evolving waveforms, migrating to pure-logic OTP (<250µm macro height) in volume maturity.
支持 (SUPPORTS)SUPPORTS
電子紙驅動晶片排除一般 BCD 製程，且遵循「演進期 MTP ➔ 成熟期 OTP」產品戰略。E-Ink DDICs strictly exclude BCD and follow the 'MTP in transition ➔ OTP in maturity' roadmap.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有全彩彩色粒子配方均已停止疊代；全彩波形算法目前仍在動態演進中。All color particle formulations have ceased iteration; full-color waveforms remain evolving.
V14VENDOR SPECIFICATION
Weebit Nano: Embedded ReRAM Qualified for Commercial IoT & Neuromorphic Analog CIM
Weebit Nano 公開技術手冊與代工廠資格（SkyWater 130nm、DB HiTek、GlobalFoundries 合作）確認：以金屬氧化物為基礎之嵌入式 ReRAM (OxRAM) 具備 100K~1M 次擦寫耐受度與 175°C 高溫保持力。不僅提供超低功耗嵌入式非揮發儲存，亦利用多階阻態 (MLC) 實現類比存算一體 (Analog Compute-in-Memory, CIM)，直接於交叉陣列中執行矩陣乘加運算，消除邊緣 AI 推論之馮諾依曼記憶體牆。 Weebit Nano technical whitepapers and commercial qualification confirm that embedded ReRAM (OxRAM) achieves 100K–1M endurance cycles and 175°C retention. Beyond non-volatile MCU storage, its multi-level conductance enables analog Compute-in-Memory (CIM), executing deep neural network matrix-vector multiplication directly within crossbar arrays to overcome the von Neumann memory wall.
支持 (SUPPORTS)SUPPORTS
阻變記憶體已跨出實驗室進入商用 PDK，並具備邊緣 AI 類比神經形態加速潛力。ReRAM has transitioned from laboratories into commercial foundry PDKs with edge AI CIM potential.
不證明 (DOES NOT PROVE)DOES NOT PROVE
全球代工廠均已標準化通用 ReRAM PDK；大容量陣列之阻態漂移與良率仍需持續校準。Universal ReRAM PDK standardization across all foundries; resistance drift in large arrays requires calibration.
V15VENDOR DATASHEET
Everspin Technologies: Enterprise STT-MRAM & Data Center Capacitor-Free Power Loss Protection (PLP)
Everspin 企業級產品手冊與技術白皮書證實：採用垂直自旋轉矩磁性穿隧接面 (pMTJ) 之 STT-MRAM 支援 DDR4、DDR3 與 xSPI 高速匯流排，提供奈秒級 (<20ns) 持久隨機寫入與 10¹⁰~10¹² 次無限擦寫耐受性。在企業級 NVMe SSD、CXL 快取擴展器與伺服器控制器中，STT-MRAM 徹底取代笨重易老化的超級電容 (Supercapacitors)，達成零延遲即時日誌寫入與無電容斷電保護 (Capacitor-Free PLP)。 Everspin commercial datasheets confirm that perpendicular MTJ (pMTJ) STT-MRAM delivers nanosecond-class (<20ns) non-volatile write latency and practically infinite endurance (10¹⁰–10¹² cycles). In enterprise NVMe SSDs and CXL memory expanders, STT-MRAM eliminates bulky supercapacitors, enabling zero-latency journal commits and maintenance-free Power Loss Protection (PLP).
支持 (SUPPORTS)SUPPORTS
STT-MRAM 在持久快取與高頻日誌寫入中相較超級電容方案具備絕對物理與可靠度優勢。STT-MRAM exhibits decisive physical and reliability advantages over supercapacitor arrays for persistent write caching.
不證明 (DOES NOT PROVE)DOES NOT PROVE
STT-MRAM 單位位元成本已能完全取代大容量 DRAM 或 3D NAND Flash。STT-MRAM cost-per-bit is currently viable to displace high-density main memory DRAM or NAND.
V16AUTOMOTIVE DISCLOSURE
Infineon Technologies: AURIX™ TC4x Microcontrollers Powered by 28nm Embedded RRAM
Infineon 官方架構手冊與 TSMC 代工合作揭露：次世代車用微控制器 AURIX™ TC4x 旗艦系列全面採用台積電 28nm eRRAM (OxRAM) 作為主控嵌入式非揮發記憶體。相較傳統 eFlash，28nm eRRAM 支援位元級單點覆寫 (Bit-level Alterability)、零區塊抹除等待時間、20 年車規高溫資料留存與 AEC-Q100 Grade 1 (150°C) 車規認證，成功突破 28nm 以下 eFlash 高光罩數與高熱預算之微縮斷崖。 Infineon's official architecture disclosures and TSMC foundry alliance demonstrate that the AURIX™ TC4x flagship automotive MCU family integrates 28nm embedded RRAM (OxRAM). Compared to legacy eFlash, 28nm eRRAM delivers bit-level overwrite capability, zero block-erase latency, 20-year retention, and AEC-Q100 Grade 1 qualification, circumventing the scaling bottlenecks of floating-gate eFlash.
支持 (SUPPORTS)SUPPORTS
新興阻變記憶體 (ReRAM) 已成功獲得車規 ASIL-D 與 AEC-Q100 Grade 1 一級車載主控認證。Emerging ReRAM has achieved ISO 26262 ASIL-D and AEC-Q100 Grade 1 qualification in tier-1 automotive MCUs.
不證明 (DOES NOT PROVE)DOES NOT PROVE
eRRAM 可無條件替換所有高溫 Grade 0 (175°C) 極限工況，極限高溫仍需依封裝測試定義。eRRAM universally satisfies Grade 0 (175°C) conditions across all profiles without specific qualification.
V17AUTOMOTIVE DISCLOSURE
STMicroelectronics: Stellar 32-bit Automotive MCU Architecture Powered by 28nm FD-SOI ePCM
STMicroelectronics 官方發布手冊確認：Stellar 車用微控制器系列整合 28nm FD-SOI 製程與嵌入式相變記憶體 (ePCM，Ge₂Sb₂Te₅ GST 合金)，具備 165°C 結溫耐受度、100K 擦寫次數與 20 年資料保持力。其內建雙分區架構 (Dual-bank A/B Partitioning) 支援真正的零停機即時空中升級 (Zero-Downtime Live OTA)，為軟體定義汽車 (SDV) 車身網關與動力網域控制器標配。 STMicroelectronics official documentation verifies that Stellar 32-bit automotive MCUs integrate 28nm FD-SOI embedded Phase Change Memory (ePCM, Ge₂Sb₂Te₅ alloy). Operating at junction temperatures up to 165°C with 100K write cycles and 20-year retention, its dual-bank partitioning supports true zero-downtime over-the-air (Live OTA) updates for Software-Defined Vehicle (SDV) architectures.
支持 (SUPPORTS)SUPPORTS
ePCM 在 28nm FD-SOI 下具備優異的車規高溫與無停機雙分區 OTA 即時寫入能力。ePCM on 28nm FD-SOI exhibits exceptional automotive thermal endurance and zero-downtime dual-bank OTA.
不證明 (DOES NOT PROVE)DOES NOT PROVE
PCM 可微縮至 FinFET 先進邏輯節點（相變材料熱干擾與重置電流限制）。PCM can scale into advanced FinFET/GAA logic nodes due to thermal cross-talk and reset current boundaries.
V18HARDWARE ROOT OF TRUST
Intrinsic ID: Quiddikey Silicon Hardware Root of Trust & Zero Factory Provisioning Architecture
Intrinsic ID 官方架構白皮書與 NIST / FIPS / PSA Certified 認證紀錄指出：Quiddikey 利用晶片原生 6T SRAM 開機微觀製程漂移作為物理指紋，搭配公開儲存之 Activation Code (Helper Data) 與 BCH 糾錯，於上電瞬間瞬態重構 256-bit 根金鑰，斷電立即銷毀。該架構免除封測廠 (OSAT) 安全無塵室金鑰注入流程，杜絕供應鏈私鑰外洩。 Intrinsic ID technical whitepapers and certification records (NIST CAVP, PSA Certified) demonstrate that Quiddikey dynamically extracts a 256-bit root key from native 6T SRAM power-up mismatch using a Fuzzy Extractor and public Activation Code (Helper Data). Erased immediately upon power-down, it eliminates costly factory key provisioning at OSATs and secures supply-chain roots of trust.
支持 (SUPPORTS)SUPPORTS
SRAM PUF 結合非機密 Helper Data 能夠在無預置金鑰條件下達成瞬態根信任重建。SRAM PUFs combined with unclassified Helper Data achieve transient root-of-trust reconstruction with zero factory keys.
不證明 (DOES NOT PROVE)DOES NOT PROVE
任何未經糾錯與隨機性驗證之一般 SRAM 均能直接作為密碼學根金鑰。Unqualified, uncharacterized generic SRAM can serve as a cryptographic root key without robust helper data ECC.
V19ENTERPRISE SECURITY
Rambus: CryptoManager™ Silicon Root of Trust & PCIe/CXL SPDM 1.3 Device Attestation
Rambus 產品規格與 DMTF 聯盟標準文獻揭露：CryptoManager™ 信任根硬體加速 DMTF SPDM 1.2/1.3 設備證明協定，並於高速 PCIe Gen5/Gen6 與 CXL 2.0/3.0 介面提供線速 IDE (Integrity and Data Encryption，AES-GCM 512/1024-bit) 硬體加解密。搭配晶圓代工廠防熔絲 OTP 記錄晶粒認證金鑰，建立由晶圓廠、封測廠到 CSP 資料中心的端到端不可偽造憑證鏈。 Rambus technical disclosures and DMTF SPDM standards verify that the CryptoManager™ Root of Trust accelerates SPDM 1.2/1.3 mutual device attestation and line-rate PCIe/CXL IDE encryption (AES-GCM). Anchored in foundry AntiFuse OTP for device unique identifiers (UID), it secures the hardware supply chain across Foundry, OSAT, and hyperscale CSP deployments.
支持 (SUPPORTS)SUPPORTS
高速互連 (PCIe/CXL) 必須仰賴硬體級 SPDM 與 IDE 防禦匯流排實體中間人竊聽。High-speed interconnects (PCIe/CXL) mandate hardware SPDM and line-rate IDE to defeat physical interposer tapping.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有伺服器周邊晶片均能承擔線速 IDE 加解密與硬體 HSM 的矽面積與功耗負擔。All server peripheral ICs can absorb the silicon area and power overhead of line-rate IDE and hardware HSMs.
C01OFFICIAL CASE
Security Through Transparency: RP2350 Hacking Challenge Results
Raspberry Pi 公開結果顯示 fault、OTP wrapper、permission 與 invasive readout 是不同路徑。FIB／PVC 已讀出相鄰 bit pair 的 OR；完整逐 bit recovery 被認為原理上可能，但未被示範。Raspberry Pi documents distinct fault, OTP-wrapper, permission and invasive-readout paths. FIB/PVC recovered the OR of adjacent bit pairs; complete per-bit recovery was considered possible in principle, but was not demonstrated.
支持 (SUPPORTS)SUPPORTS
Bit-cell opacity 不應是最後一道 confidentiality boundary；成功 readout 的後果必須由 composed controls 限制。Bit-cell opacity should not be the final confidentiality boundary; composed controls must constrain the consequence of successful readout.
不證明 (DOES NOT PROVE)DOES NOT PROVE
所有 OTP 都有相同漏洞、完整 RP2350 secret 已被逐 bit 恢復，或 Secure Storage target configuration 已具 attack resistance。That every OTP shares the flaw, that the complete RP2350 secret was recovered per bit, or that a target Secure Storage configuration is attack-resistant.
找不到符合條件的證據。No evidence matches the current query.
引用政策：Citation policy: 本 Ledger 以 primary／first-party sources 為主。供應商互相比較的內容只當作「該供應商的公開立場」，不當成獨立驗證。Google Patents 用於提供原始專利全文；產品是否實作某專利需另外證明。任何要進入 datasheet、合約或正式 first-party 簡報的定量安全主張，仍須由 sponsoring organization 的 legal、product-security 與 release owners，以及適用的 NDA evidence 完成核准。This ledger prioritizes primary and first-party sources. Vendor comparisons are treated as that vendor's public position, not independent validation. Google Patents provides original patent text; product implementation of a patent requires separate evidence. Quantified security claims entering a datasheet, contract or formal first-party presentation require approval from the sponsoring organization’s legal, product-security and release owners, together with any applicable NDA evidence.
最值得相信的定位，
是能看見證據邊界的定位The most credible positioning
makes its evidence boundary visible
回到研究正文，從 cell physics、read path、光熱可觀測性與 power-off state，形成可上台、也能接受工程審查的 Secure Storage 敘事。Return to the paper and turn cell physics, read path, optical/thermal observability and power-off state into a Secure Storage narrative that survives both the stage and engineering review.
返回研究正文Return to the research paper 返回 Secure StorageReturn to Secure Storage